It is known to provide data processing systems utilizing the technique of register renaming. In such systems there exists a pool of physical registers which can be mapped to architectural registers as specified within instructions of the instruction set of the data processing system concerned. One example use of such register renaming techniques is to facilitate out-of-order processing. In this context, register renaming allows the system to cope with write-after-write hazards and write-after-read hazards and provide a mechanism for recovering architectural state should processing not proceed as predicted, e.g. as a consequence of a mis-predicted branch instruction, as a consequence of an abort, or some other exception.
It will be appreciated that one feature of such register renaming techniques is that more physical registers are provided than there are architectural registers which may be specified. As the degree of speculation increases and the parallelism increases, then there is a general increase in the required number of physical registers in order that this should not become a limiting factor. As an example, if an instruction requires renaming but all of the physical registers provided are already in use for other mappings, then the instruction concerned cannot be subject to register renaming, and the processing will stall until physical registers become available. One solution to this is to increase the number of physical registers provided. However, this solution disadvantageously increases the circuit area and power consumption of the system concerned.
It is known within data processing systems to provide instructions within an instruction set that are conditional upon the outcome of preceding instructions. This is often achieved by associating condition codes with a particular instruction. The condition codes are set by preceding processing outcomes and then the instruction concerned is executed if the condition codes which are in effect at the time the instruction has its condition codes checked indicate that the condition codes associated with the instruction have been passed. An example of such instructions are the instructions of the ARM instruction set used by processors designed by ARM Limited Cambridge England. The ARM instructions have a four bit condition code associated with them which specify conditions upon which they are to be executed, e.g. execute if the zero flag is set.